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Go to the source code of this file.
Macros | |
#define | USR_MODE 16 |
ARM Program Status Register (CPSR) More... | |
#define | IRQ_MODE 18 |
#define | FIQ_MODE 17 |
#define | SVC_MODE 19 |
#define | ABT_MODE 23 |
#define | UND_MODE 27 |
#define | SYS_MODE 31 |
#define | HYP_MODE 0x1a |
#define | MODE_MASK 0x1f |
#define | IRQ_BIT (1 << 7) |
#define | FIQ_BIT (1 << 6) |
#define | ASYNC_ABORT_BIT (1 << 8) |
#define | ELR .long 0xe12ef30e |
ARM Model-Specific Instructions. More... | |
#define | ERET .long 0xe160006e |
eret More... | |
#define | PAGESHIFT 12 |
ARM Memory Constants. More... | |
#define | DIRSHIFT 20 |
Page table bit shift. More... | |
#define | PAGESIZE 4096 |
ARM uses 4K pages. More... | |
#define | PAGEDIR_MAX 4096 |
Number of entries in the first-level page table. More... | |
#define | PAGEDIR_SIZE (PAGEDIR_MAX * sizeof(u32)) |
#define | PAGETAB_MAX 256 |
Number of entries in a second-level page table. More... | |
#define | PAGETAB_SIZE (PAGETAB_MAX * sizeof(u32)) |
#define | PAGETAB_SPAN (PAGETAB_MAX*PAGESIZE) |
#define | PAGEMASK 0xfffff000 |
Mask to find the page. More... | |
#define | SECTIONMASK 0xfff00000 |
Mask for large 1MiB section mappings. More... | |
#define | MEMALIGN 4 |
Memory address alignment. More... | |